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Ordering number : ENN8095
SANYO Semiconductors
DATA SHEET
Monolithic Digital IC
LB11693
Overview
Three-Phase Brushless Motor Driver for 24 V Fan Motors
The LB11693 reduces motor noise by imparting a slope to the output current when switching the phase to which power is applied. This motor driver includes an automatic recovery constraint protection circuit and is optimal for driving 24 V fan motors.
Functions and Features
* * * * * * * * * Soft phase switching + direct PWM drive PWM control based on both a DC voltage input (the CTL voltage) and a pulse input Provides a 5 V regulator output One Hall-effect sensor FG output Integrating amplifier Automatic recovery constraint protection circuit (on/off = 1/14), RD output Current limiter circuit LVSD circuit Thermal protection circuitt
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter Supply voltage Output current Allowable power dissipation 1 Allowable power dissipation 2 Operating temperature Storage temperature Symbol VCC max IO max Pd max1 Pd max2 Topr Tstg T 500 ms Independent IC With an infinite heat sink Conditions Ratings 30 1.8 3 20 -30 to +100 -55 to +150 Unit V A W W C C
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
N1004TN (OT) No.8095-1/12
LB11693
Allowable Operating Conditions at Ta = 25C
Parameter Supply voltage range Constant voltage output current RD output current FG output current Symbol VCC IREG IRD IFG Conditions Ratings 9.5 to 28 0 to -30 0 to 10 0 to 10 Unit V mA mA mA
Electrical Characteristics at Ta = 25C, VCC = VM = 24 V
Parameter Current drain 1 Current drain 2 Output Block Output saturation voltage 1 Output saturation voltage 2 Output leakage current High side diode forward voltage 1 High side diode forward voltage 2 5 V Constant Voltage Output Output voltage Line regulation Load regulation Hall Sensor Amplifier Input bias current Differential-mode input voltage range Common-mode input voltage range Input offset voltage CSD Pin High-level output voltage Low-level output voltage External capacitor charge current External capacitor discharge current Charge/discharge current ratio Undervoltage Protection Circuit (LVS pin) Operating voltage Release voltage Hysteresis Current Limiter Circuit (RF pin) Limit voltage Thermal Protection Operation Thermal protection operating temperature Hysteresis CTL Amplifier Input offset voltage Input bias current Common-mode input voltage range High-level output voltage Low-level output voltage Open-loop gain PWM Oscillator Circuit High-level output voltage Low-level output voltage Amplitude External capacitor charge current Oscillator frequency TOC Pin Input voltage 1 Input voltage 2 Input voltage 1L Input voltage 2L Input voltage 1H Input voltage 2H VTOC1 VTOC2 VTOC1L VTOC2L VTOC1H VTOC2H Output duty: 100% Output duty: 0% Design target value, when VREG = 4.7 V, 100% Design target value, when VREG = 4.7 V, 0% Design target value, when VREG = 5.3 V, 100% Design target value, when VREG = 5.3 V, 0% 2.72 1.07 2.72 1.07 3.08 1.21 3.0 1.3 2.80 1.17 3.20 1.33 3.30 1.45 2.90 1.27 3.30 1.45 V V V V V V VOH (PWM VOL (PWM) V (PWM) ICHG f (PWM) VPWM = 2.1 V C = 2200 pF 2.75 1.1 1.5 -125 15.5 3.0 1.3 1.7 -90 19.5 3.25 1.4 2.0 -70 27.0 V V Vp-p A kHz VIO (CTL) IB (CTL) VICM VOH (CTL) VOL (CTL) G (CTL) ITOC = -0.2 mA ITOC = 0.2 mA f (CTL) = 1 kHz 45 -10 -1 0 VREG - 1.2 VREG - 0.8 0.8 51 1.05 +10 +1 VREG - 1.7 mV A V V V dB TSD TSD Design target value (junction temperature) Design target value (junction temperature) 150 170 40 C C VRF VCC - VM 0.45 0.5 0.55 V VSDL VSDH VSD 3.6 4.1 0.35 3.8 4.3 0.5 4.0 4.5 0.65 V V V VOH (CSD) VOL (CSD) ICSD1 ICSD2 RCSD Charge current/discharge current 2.75 0.85 -3.3 0.09 3.0 1.0 -2.4 0.17 14 3.25 1.15 -1.4 0.23 V V A A times IB (HA) VHIN VICM VIOH Sine wave input Differential input, 50 mVp-p Design target value 50 1.5 -20 2 10 350 VREG - 1.0 20 A mVp-p V mV VREG VREG1 VREG2 IO = -5 mA VCC = 9.5 to 28 V IO = -5 to -20 mA 4.7 5.0 30 20 5.3 100 100 V mV mV VOsat1 VOsat2 IOleak VD1 VD2 ID = 0.7 A ID = 1.5 A 1.25 1.9 IO = 0.7 A, VO (SINK) + VO (SOURCE) IO = 1.5 A, VO (SINK) + VO (SOURCE) 1.5 2.2 2.05 2.9 100 1.65 2.5 V V A V V Symbol ICC1 ICC2 Stop mode Conditions Ratings min typ 10 4.0 max 13.5 5.5 Unit mA mA
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LB11693
Continued from preceding page.
Parameter RD Pin Low-level output voltage Output leakage current FG Pin Low-level output voltage Output leakage current FGFIL Pin Charge current Discharge current FG Amplifier Schmitt Block (IN1) Amplifier gain Hysteresis S/S Pin High-level input voltage range Low-level input voltage range Input open voltage Hysteresis High-level input current Low-level input current PWMIN Pin Input frequency range High-level input voltage range Low-level input voltage range Input open voltage Hysteresis High-level input current Low-level input current F/R Pin High-level input voltage range Low-level input voltage range Input open voltage Hysteresis High-level input current Low-level input current VIH (FR) VIL (FR) VIO (FR) VIS (FR) IIH (FR) IIL (FR) VF/R = VREG VF/R = 0 V 2.0 0 VREG - 0.5 0.16 -10 -165 0.25 0 -115 VREG 1.0 VREG 0.34 +10 V V V V A A f (PI) VIH (PI) VIL (PI) VIO (PI) VIS (PI) IIH (PI) IIL (PI) VPWMIN = VREG VPWMIN = 0 V -170 2.0 0 2.6 0.16 2.9 0.25 100 -130 50 VREG 1.0 3.2 0.34 130 kHz V V V V A A VIH (SS) VIL (SS) VIO (SS) VIS (SS) IIH (SS) IIL (SS) VS/S = VREG VS/S = 0 V -170 2.0 0 2.6 0.16 2.9 0.25 100 -130 VREG 1.0 3.2 0.34 130 V V V V A A G (FG) VIS (FG) Design target value Design target value, input equivalent 7 8 times mV IFGFIL1 IFGFIL2 -7 3 -5 5 -3 7 A A VOL (FG) IL (FG) IFG = 5 mA VFG = 28 V 0.1 0.3 10 V A VOL (RD) IL (RD) IRD = 5 mA VRD = 28 V 0.1 0.3 10 V A Symbol Conditions Ratings min typ max Unit
Package Dimensions
unit : mm 3147C
Pdmax -- Ta
24
28
15
Allowable power dissipation, Pdmax -- W
With an infinite heat sink
20
R1.7
12.7 11.2
8.4
16
0.4
1
20.0 26.75
14
12
8
8.0
4.0
4.0
4 3 0 -30
Independent IC
1.2 0 30 60 90 120
(1.81)
1.78
0.6
1.0
SANYO : DIP28H (500mil)
Ambient temperature, Ta -- C
No.8095-3/12
LB11693
Truth Table
Source Sink 1 2 3 4 5 6 OUT2 OUT1 OUT3 OUT1 OUT3 OUT2 OUT1 OUT2 OUT1 OUT3 OUT2 OUT3 F/R = L IN1 H H H L L L IN2 L L H H H L IN3 H L L L H H IN1 L L L H H H F/R = H IN2 H H L L L H IN3 L H H H L L
Pin Assignment
OUT1 28 F/R 27 IN3+ 26 IN3- 25 IN2+ 24 IN2- 23 IN1+ 22 IN1- 21 GND1 20 PWM 19 TOC 18 EI- 17 EI+ 16 S/S 15
LB11693
1 OUT2
2
3
4 VD
5 VCC
6 VM
7 VREG
8 LVS
9 FGFIL
10 FC
11 CSD
12 FG
13 RD
14 PWMIN
OUT3 GND2
No.8095-4/12
LB11693
Pin Functions
Pin No. 28 1 2 Symbol OUT1 OUT2 OUT3 Function Equivalent circuit
VCC
Motor drive outputs
VD 300 VM
4 6
3
GND2
Motor drive output system ground
4
VD
Low side output transistor drive current supply
1
2
28
6
VM
Motor drive output power supply and output current detection Connect the resistor Rf between this pin and VCC. The output current will be limited to the current value set by the equation IOUT = VRF/Rf. Power supply for systems other than the motor drive output
3
5
VCC
VCC
7
VREG
5 V regulator output Insert a capacitor (about 0.1 F) between this pin and ground for stabilization.
7
VREG
8
LVS
Undervoltage protection voltage detection To detect VREG, connect this pin to VREG. To detect VCC, set the detection voltage by inserting a zener diode in series.
52 k
8
9.5 k
VREG
9
FGFIL
FG filter connection This pin is normally left open. If noise on the FG signal is a problem, insert a capacitor between this pin and ground.
300
9
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No.8095-5/12
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Continued from preceding page.
Pin No. Pin Name Pin Description Equivalent circuit
VREG
300
10 FC Control loop frequency characteristics correction Insert a capacitor between this pin and ground.
10
VREG
11
CSD
Sets the operating time constant for the constraint protection circuit.
300 11
VREG 12
12 FG Hall sensor FG output (This is an open-collector output.)
VREG
Motor constraint state detection (This is an open-collector output.) This pin outputs a high level if the motor is mechanically constrained, and it outputs a low level when the motor is turning.
13
13
RD
VREG
14
PWM IN
PWM pulse input When low, the outputs are turned on, and when high or open, the outputs are turned off. When these pins are used for control, connect the EI- pin to ground and the EI+ pin to the TOC pin.
30 k 5 k 14 40 k
Continued on next page.
No.8095-6/12
LB11693
Continued from preceding page.
Pin No. Pin Name Pin Description Equivalent circuit
VREG
15
S/S
Motor start/stop control A low level selects start mode, and a high level or open selects stop mode.
30 k 5 k 15 40 k
VREG
16 17
EI+ EI-
Control amplifier noninverting input Control amplifier inverting input
16
300
300
17
VREG
18
TOC
PWM waveform comparison (Control amplifier output)
18
PWM comparator VREG
40 k
19
PWM
Sets the PWM oscillator frequency. Insert a capacitor between this pin and ground. A value of C = 2200 pF sets the frequency to be about 20 kHz.
200 2 k
19
Continued on next page.
No.8095-7/12
LB11693
Continued from preceding page.
Pin No. 20 Pin Name GND1 Pin Description Ground for systems other than the motor drive output Equivalent circuit
VREG
22 21 24 23 26 25
IN1+ IN1- IN2+ IN2- IN3+ IN3-
Hall-effect sensor inputs When IN+ > IN-, the input is seen as a high level, and when the reverse condition is true, it is seen as a low level. An amplitude of over 50 mVp-p (differential) is desirable as the Hall input signal. If noise on the Hall signals is a problem, insert capacitors between the IN+ and IN- inputs.
21
23
25
300
300
22
24
26
VREG
27
F/R
Forward/reverse control A low level specifies forward and a high level or open specifies reverse.
40 k 3.5 k 27
No.8095-8/12
FG Vcc
RD
EI- FG FC LVS RD CIRCUIT Vcc TSD CIRCUIT LVSD CSD RD
TOC
- FG CSD
EI+
CTL
+
Equivalent Circuit Block Diagram
CTL AMP
VD CURR COMP LIM VM
Rd
PWM
PWM
Rf
PWMIN CONTROL CIRCUIT
LB11693
PWMIN
OUT1
DRIVER FILTER HALL AMP & MATRIX F/R
BGP
VREF
OUT2
GND1
5VREG
S/S
OUT3
VREG VREG
S/S F/R
FGFIL
IN1
IN2
IN3
GND2
No.8095-9/12
LB11693
Functional Description 1. Output Drive Circuit This IC reduces motor vibration and noise by smoothly switching the output current when switching phases. Since control of the change (slope) in the output current during phase switching uses the slope of the Hall sensor input waveform, if the slope of the Hall sensor input waveform is too steep, the changes in the output current during phase switching will also be too steep. This will reduce the noise and vibration minimizing effect of this design. Thus care is required with regard to the slope of the Hall sensor input waveform. Motor speed control is implemented by PWM switching of the low side output transistor. The drive output is adjusted by changing the duty. The LB11693 includes the diode between OUT and VM used for the regenerative current when the PWM signal is off. When the slope (amplitude) of the Hall sensor input waveform is large, if the circuit is used with a large current, the parasitic diode between OUT and ground will operate due to the low side kickback during phase switching. If waveform disruptions or other problems occur, add an external rectifying diode or Schottky diode between OUT and ground. 2. Power Supply Stabilization Since this IC uses a PWM switching technique, the power supply line level can be disturbed easily. Electrolytic capacitors with adequate capacitance to stabilize the power supply lines must be inserted between VCC and ground. The power supply lines will be especially subject to disturbance if diodes are inserted in the power supply lines to prevent damage if the power supply is connected with reversed polarity. Here, even larger capacitances should be used. The connected electrolytic capacitors must be placed as close to the IC pins (VCC, VM, and the two ground pins) as possible. If the heat sink or some other obstacle prevents the electrolytic capacitors from being connected close to the IC, ceramic capacitors with a capacitance of about 0.1 F must be connected near the pins. 3. VREG Pin The VREG pin is both the 5 V regulator output and the power supply for the IC's internal control circuits. Therefore, a capacitor with a capacitance of at least 0.1 F must be connected between VREG and ground. The ground side of the connected capacitor must be connected to the GND1 pin with a line that is as short as possible. 4. FC Pin The capacitor connected to the FC pin is required to correct the control loop frequency characteristics. (Use a value of about 0.1 F.) 5. VD Pin The VD pin supplies the low side output transistor drive current (about 0.1 A, maximum). The IC internal power consumption can be suppressed by connecting a resistor between the VCC and VD pins to divide the power consumption due to the low side transistor drive current. The IC internal power consumption due to the drive current can be made smaller to the extent the VD pin voltage is lowered. However, a voltage of 4 V or higher must be assured for the VD pin voltage. When used with VCC = 24 V, insert a resistor of between 50 (0.5 W) and 100 (1 W) between the VCC and VD pins. 6. Hall Input Signals A signal input with an amplitude (differential) of 50 mVp-p or higher is required for the Hall inputs. If disturbances in the output waveform occur due to noise, capacitors must be connected across the Hall input pins (the + and - sides). 7. Current Limiter Circuit The current limiter circuit limits the output current peak value to a level determined by the equation I = VRF/Rf (VRF = 0.5 V typical, Rf: current detection resistor). This circuit limits the current by controlling the low side output transistor PWM at the PWM frequency determined by the PWM pin external capacitor. In particular, it reduces the on duty of the PWM signal. 8. Forward/Reverse Direction Switching This IC is designed with the assumption that the motor direction (forward or reverse) will not be switched while the motor is turning. We recommend operating this IC with the F/R pin held fixed at either the low or high level. When this pin is left open, the internal pull-up resistor (about 40 k) will set the pin to the high level. However, if there are large fluctuations in signal levels in the circuit, this pull-up resistor should be strengthened by adding an external resistor. If a direction switching operation is performed while the motor is turning, large currents will flow due to the braking operation. However, this IC's current limiter circuit cannot limit these braking currents. Thus direction switching is only
No.8095-10/12
LB11693
possible if the braking current is limited to be under Iomax (1.8 A) by the motor coil resistance or other factors. Also, since a transient through current will flow at the instant the direction is switched if the direction switching operation is performed just from the F/R pin, a period where drive is turned off must be provided when switching directions. Through currents must be prevented by setting the IC to the stop state with the S/S pin or TOC pin to provide a drive off period where the duty due to the PWMIN pin is set to 0% and switching the F/R pin during that period. 9. Power Saving Circuit This IC goes to a low-power mode (power saving state) when set to the stop state with the S/S pin. In the power saving state, the bias currents in most of the circuits are cut off. However, the 5 V regulator output is still provided in the power saving state. 10. Notes on the PWM Frequency The PWM frequency is determined by the capacitor C (F) connected to the PWM pin. fPWM 1/(23400 x C) It is preferable to use a frequency in the range 15 kHz to 25 kHz for the PWM frequency. The connected capacitor must be connected to the GND1 pin with a line as short as possible. 11. Control Methods The output duty can be controlled by either of the following methods * Control based on comparing the TOC pin voltage to the PWM oscillator waveform The low side output transistor duty is determined according to the result of comparing the TOC pin voltage to the PWM oscillator waveform. When the TOC pin voltage is 1.3 V or lower, the duty will be 0%, and when it is 3.0 V or higher, the duty will be 100%. Since the TOC pin is the output of the control amplifier (CTL), a control voltage cannot be directly input to the TOC pin. Normally, the control amplifier is used as a full feedback amplifier (with the EI- pin connected to the TOC pin) and a DC voltage is input to the EI+ pin (the EI+ pin voltage will become equal to the TOC pin voltage). When the EI+ pin voltage becomes higher, the output duty increases. Since the motor will be driven when the EI+ pin is in the open state, a pull-down resistor must be connected to the EI+ pin if the motor should not operate when EI+ is open. When TOC pin voltage control is used, a low-level input must be applied to the PWMIN pin or that pin connected to ground. * Control based on a pulse signal input to the PWMIN pin A pulse signal with a frequency in the range 15 to 25 kHz can be input to the PWMIN pin, and the duty of the low side output transistor can be controlled based on the duty of that input signal. Note that the output is on when a low level is input to the PWMIN pin, and off when a high level is input. When the PWMIN pin is open it goes to the high level input and the output is be turned off. When controlling motor operation from the PWMIN pin, the EI- pin must be connected to ground, and the EI+ pin must be connected to the TOC pin. 12. Undervoltage Protection Circuit The undervoltage protection circuit turns the low side output transistor off when To the power supply the LVS pin voltage falls below the minimum operation voltage (about 3.8 V). level to be detected The operating voltage detection level is set up for 5 V systems. The detected voltage level can be increased by shifting the voltage by inserting a zener diode To the LVS pin in series with the LVS pin. The LVS influx current during detection is about 65 A. To minimize the effect of sample-to-sample variations in the zener voltage, the current flowing in the zener diode must be increased thus stabilizing the rise in the zener diode voltage. If this is required, insert a resistor between the LVS pin and ground. If the LVS pin is left open, the internal pull-down resistor will result in the IC seeing a ground level input, and the output will be turned off. Therefore, a voltage in excess of the LVS circuit clear voltage (about 4.3 V) must be applied to the LVS pin if the application does not use the undervoltage protection circuit. The maximum rating for the LVS pin applied voltage is 30 V. 13. Constraint Protection Circuit When the motor is physically constrained (held stopped), the CSD pin external capacitor is charged (to about 3.0 V) by a constant current of about 2.4 A and is then discharged (to about 1.0 V) by a constant current of about 0.17 A. This process is repeated, generating a sawtooth waveform. The constraint protection circuit turns motor drive (the low side
No.8095-11/12
LB11693
output transistor) on and off repeatedly based on this sawtooth waveform. Motor drive is on during the period the CSD pin external capacitor is being charged from about 1.0 V to about 3.0 V, and motor drive is off during the period the CSD pin external capacitor is being discharged from about 3.0 V to about 1.0 V. The IC and the motor are protected by this repeated drive on/off operation when the motor is physically constrained. When a 0.47 F capacitor is connected to the CSD pin, this repeated operation will turn motor drive on for about 0.4 seconds and off for about 5.5 seconds. When the motor is turning, the CSD pin is held at a certain fixed voltage (which varies depending on the motor speed) by the CSD pin external capacitor being charged and discharged by two processes. One is the constant current (about 2.4 A) charge current, and the other is a roughly 10 s discharge pulse generated internal in the IC when the Hall sensor input IN1 changes state (on rising and falling edges on the FG output). Since the Hall sensor input IN1 does not change state when the motor is not turning, discharge pulses are not generated, and the CSD pin external capacitor is charged by the approximately 2.4 A constant current until it reaches about 3.0 V. At that point, the constraint protection circuit operates. The constraint protection state is cleared if the motor constraint is released. When the motor turns at an extremely low rate, the CSD pin voltage during this motor rotation will be held at a relatively high voltage, and the constraint protection circuit will operate if this reaches the roughly 3.0 V threshold level. Since the constraint protection circuit may operate if the Hall sensor input IN1 frequency falls below about 10 Hz, care is required when using the constraint protection circuit with a motor that turns slowly. Connect the CSD pin to ground if the constraint protection circuit is not used.
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products(including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be expor ted without obtaining the expor t license from the author ities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of November, 2004. Specifications and information herein are subject to change without notice.
PS No.8095-12/12

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